Reset Timing (Inactive Clock Polarity Low Shown)
CS
SCK
RESET
t REC
t RST
t CSS
SO
HIGH IMPEDANCE
HIGH IMPEDANCE
SI
Command Sequence for Read/Write Operations (Except Status Register Read)
SI
CMD
8 bits
8 bits
8 bits
MSB
r X X X XXXX
XXXX XXXX
XXXX XXXX
LSB
Reserved for
larger densities
Page Address
(PA12-PA0)
Byte/Buffer Address
(BA9-BA0/BFA9-BFA0)
Notes:
1.
“ r ” designates bits reserved for larger densities.
10
2.
3.
It is recommended that “ r ” be a logical “ 0 ” for densities of 32M bit or smaller.
For densities larger than 32M bit, the “ r ” bits become the most significant Page Address bit for the appropriate density.
AT45DB321
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